Recently, remarkable developments have occurred in the field of microcomputers having built-in capacitors of high dielectric constant materials. Such microcomputers contribute to reducing unnecessary radiation that causes electro-magnetic interference. Equally remarkable are developments in the field of ferroelectric non-volatile RAM which facilitates low-voltage operation and high read/write speed. The high dielectric constant materials or ferroelectric materials are made mainly of sintered metal oxide, and contain a substantial amount of very reactive oxygen. In forming a capacitor with such dielectric film, material for its electrodes must be least reactive; thus, precious metals such as platinum (Pt), palladium (Pd), etc. must be used.
In the prior art, platinum and palladium etching has been conducted by means of isotropic etching, such as wet etching with aqua regia or by ion milling with Ar gas. Because of the nature of isotropic etching, using wet etching with aqua regia and ion milling causes deteriorated processing accuracy. Furthermore, an additional problem with ion milling occurs because the etching speed on platinum, which is to form the electrode, and on silicon oxide, etc., which is underneath the platinum, are almost the same, the silicon oxide is also etched during ion milling.
In order to increase processing accuracy, research and development has been quite active in the precision processing technology with respect to the platinum layer and metal oxide dielectric thin film by means of a dry etching process, where Cl.sub.2 and HBr are used as the etching gas (see, Extended Abstracts, Autumn Meeting 1991, The Japan Society of Applied Physics, 9P-ZF17, p. 516; Extended Abstracts, Spring Meeting 1993, The Japan Society of Applied Physics, 30a-ZE-3, pp. 577).
A conventional method for manufacturing semiconductor devices is described with reference to FIGS. 8(a)-(c). As shown in FIG. 8(a), a silicon oxide layer 4 is formed as an insulation layer on top of a silicon substrate 3 on which a circuit element 1 and a wiring 2 are already shaped. Over the silicon oxide layer 4 is a first platinum layer 5, a film of high dielectric constant material or ferroelectric material (hereinafter referred to as dielectric film) 6 and a second platinum layer 7.
The silicon oxide layer 4 reflects unevenness due to the circuit element 1 or wiring 2 already shaped on the silicon substrate 3 to have a hollow 8 or protrusion 9 on its surface, as shown in FIG. 8(a). Because dielectric film 6 is spin-coated on the uneven surface of silicon oxide layer 4, thickness of the dielectric film 6 is large at the hollow 8, and small at the protrusion 9.
Next, as shown in FIG. 8(b), top electrode 7a and capacitance insulation film 6a are formed by dry-etching the second platinum layer 7 and dielectric film 6 with Cl.sub.2, HBr as the etching gas. The facility used for the etching is a magnetron reactive ion etching (RIE) mode dry etcher. Through the same etching procedure the first platinum layer 5 is etched to form a bottom electrode 5a; and a capacitor is thus formed. A layer to protect the capacitor, electrode wiring and protection layer for the electrode wiring are formed through process steps not shown in the figure; and a semiconductor device is completed.
An example of the etching characteristics on platinum, high dielectric constant material (BaSrTiO.sub.3, hereinafter referred to as BST) and resist is explained below when Cl.sub.2 is used as the etching gas. FIG. 9 shows dependence of the etching speed of platinum, BST and resist to RF power. Where, the horizontal axis denotes RF power, the vertical axis denotes etching speeds of platinum, BST and resist.
The facility used for the etching is magnetron RIE mode dry etcher. The etcher conditions are: Cl.sub.2 gas flow 20 sccm, gas pressure 1 Pa, RF power within a range between 200 W and 600 W, wafer temperature during etching below 20.degree. C. as its back surface is cooled with He.
FIG. 9 exhibits that platinum etching speed is increased from 30 nm/min. to 100 nm/min., BST etching speed is increased from 20 nm/min. to 70 nm/min. and resist etching speed is increased from 200 nm/min. to 350 nm/min., when RF power is raised from 200 W to 600 W.
When, the platinum/resist etching speed ratio increases from about 0.15 to about 0.29 along with the increase of RF power from 200 W to 600 W. The BST/resist etching speed ratio also increases from about 0.10 to about 0.20. Under any condition, the etching speed of resist is much faster than that of platinum and BST.
The time required to etch the platinum layer (200 nm thick) and BST (200 nm thick) with RF power at 600 W is 4 min. 52 sec. The etching quantity of the resist during this time span is calculated from the resist etching speed to be 1703 nm, a very large value. This means that, if the resist layer is thinner than 1700 nm, the resist is entirely etched while etching is conducted on the platinum and BST. If this is to be prevented, a thick resist layer of more than about 3 .mu.m thick has to be used.
As described above, however, when Cl.sub.2 etching gas is used, the etching speed of resist is very high relative to that of platinum and BST. Consequently, while platinum and BST are being etched for a certain required thickness, the resist layer is also etched significantly. In order to prevent this from occurring a thick-layer resist needs to be used. But the thick-layer resist affects the definition level of the mask pattern at photolithography, rendering the formation of a fine pattern very difficult.
The etching speed of the silicon oxide layer is about 2.5 times faster than that of the platinum layer. So, as shown in FIG. 8(c), during formation of bottom electrode 5a, its underlayer, the silicon oxide layer 4 is significantly etched.
The problem with etching the silicon oxide layer 4 is illustrated in FIGS. 8(b) and 8(c). Before the thick part of first platinum layer 5 (located on the hollow 8 of silicon oxide layer 4) is completely etched off, the etching gas, which already etched the thin part of first platinum layer 5 (located on the extrusion 9 of silicon oxide layer 4), quickly attacks the underlying silicon oxide layer 4 to etch it off, and when gate electrode 1a of circuit element 1 and wiring 2 are exposed, they are also etched, rendering the transistor and other circuit element 1 inoperable.
In the case of ion milling where Ar gas is used as the etching gas, because the ratio of the etching speed of the second platinum layer 7 and dielectric film 6 to the etching speed of the silicon oxide layer 4 is low, when forming a capacitor in two separate etching process steps (e.g., etching on the second platinum layer 7 and dielectric film 6, and then on the first platinum layer 5), it is extremely difficult to stop the etching procedure so that the first platinum layer is not etched.
In the case of dry etching on platinum and ferroelectric material, because of its slow etching speed, the throughput of the production facility is poor.